The invention relates to a single-channel communication bus system. Such a system is understood to mean one which has the data travelling serially along one physical connection. The data may be self-clocking. In such case either one lead is present, or alternatively two wires carrying, for example, symmetric signals. The data may, alternatively, be not self-clocking. In that case a further lead is present for transferring synchronizing clock signals. Various bus systems have been described in the art; an exemplary state is given by U.S. Pat. No. 4,429,384 or U.S. patent application Ser. No. 317,693, both to the same assignee as this application and herein incorporated by reference. According to the first reference, the data itself is self-clocking, the bus interconnection has a logic-AND-function (wired-AND), each bit cell has two transitions, the position of the second thereof representing the data content of the bit in question. The first transition is always near the start of the bit cell. Provisions have been made for an arbitraging organization: if two stations send simultaneously different bit values to the bus, the logic-AND-function will see to it that all stations receive a logic "zero". Thus the logic "one" is masked and the station sending the "one" has lost the arbitrage and is thus forced to relinquish control of the bus.
Transferring of a message in the above described communication system and various other systems necessitates to answer a message with an acknowledge. Such acknowledgement is then usually sent by one (or more) stations acting as slaves. Such slave could function either as a slave receiver or as a slave transmitter (the latter for example if an addressed memory operates in a reading access).